In the interconnect technique of an integrated circuit, an ILD layer is typically used for separating a metal wiring layer from an active layer of a semiconductor device, or from another metal wiring layer. The electric connection between the metal wiring layers, or between the metal wiring layer and the active layer of the semiconductor device can be implemented by means of conductive vias through the ILD layer.
The ILD layer having a planar surface is beneficial for depositing and patterning subsequent layers, and also is beneficial for electrical isolation between the metal wiring layer and the underlying layer of the semiconductor device, and further is beneficial for forming multi-level metal wiring interconnections. The ILD layer having a planar surface also improves mechanical strength and reliability of the semiconductor device, because there is no defect such as holes occurring during later-layer deposition.
To form an ILD having a planar surface, the ILD layer is subjected to Chemical Mechanical Polishing (CMP) after the ILD layer is deposited, which increase complexity and costs of the manufacturing process, especially for a first insulating layer for isolating the gate stack structure with a super small gate length.
The CMP process can be replaced by a dual-layer ILD layer structure provided by firstly depositing a conformal insulating layer, such as a low temperature oxide (LTO) layer, and then depositing a spin-on glass (SOG) layer thereon, wherein the LTO layer forms a conformal layer which covers a large area of a wafer, and the SOG layer further fills recesses on the surface, and thus a substantially planar surface can be obtained.
Then, in order to further form a planar surface, the SOG layer can be etched back by dry etching, such as reactive ion etching (RIE), so as to planarize its surface. Typically, a mixture of trifluoromethane (CHF3), tetrafluoromethane (CF4) and Oxygen (O2) is used as an etching gas in the RIE.
In U.S. Pat. No. 5,316,980A of Shinichi Takeshiro etc., it is further proposed that a mixture of trifluoromethane (CHF3) and hexafluoroethane (C2F6) can be used as the etching gas, so that an etching rate of the organic SOG layer is lower than that of an underlying SiO2 layer. Consequently, a planar surface of the structure can still be provided even in a case that the underlying SiO2 layer is partly exposed.
However, the SOG layer etching method mentioned above actually can not achieve global planarization. It has been found that the etching rate of the SOG layer at the center of the wafer is lower than that at the edge of the wafer. As will be described, the etched SOG layer has a convex etching profile. As a result, the edge of the wafer has to be discarded since the thickness of SOG layer at the edge can not achieve the desired planarization and should be discarded, which reduces an available area of the wafer for manufacturing the semiconductor device.